This invention relates to memory cells and more particularly relates to content addressable memory cells.
Many memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory access. The time required to find an item stored in memory can be reduced considerably if the stored data item can be identified for access by the content of the data itself rather than by its address. Memory that is accessed in this way is called content-addressable memory (CAM). CAM provides a performance advantage over other memory search algorithms (such as binary and tree-based searches or look-aside tag buffers) by comparing the desired information against the stored data simultaneously, often resulting in an order-of-magnitude reduction of search time.
A CAM cell is the basic circuit determining the speed, size and power consumption of a CAM system. Known CAM cells require a substantial number of transistors that consume power and require a substantial amount of area on a chip. In addition, match circuitry employed in known CAM cells requires a substantial amount of time for proper operation. This invention addresses these problems and provides a solution.
U.S. Pat. No. 6,222,780 (Takahashi, filed Mar. 9, 2000), describes an SRAM memory cell in which transistors 11 and 12 are turned off, and are said to allow an off-leak current to flow therethrough to maintain the on- or off-state of driver nMOS transistors 13 and 14. However, the off-state of the transistors 11 or 12 gives only a single compensation point. In real silicon, the leakage of the transistor 13 or 14 can vary over a very wide range due to changes in process corners, temperatures and power supply variation. In many applications, for example mobile devices, the voltage supply is intentionally kept low to save power in the sleep mode or normal operation.
In the 0.13 micrometer (um) and future process technologies, Ioff and gate leakage are becoming significant factors. Referring to FIG. 3, of U.S. Pat. No. 6,181,591 (Miyatake et al., issued Jan. 30, 2001, the “'591 patent”), node 18 will never be set to a full VDD supply voltage because NMOS transistors 16 and 17 can not pass a full VDD voltage. As a result, match transistor 25 always is partially on. Since many match transistors (e.g., 256) may be connected to the match line, arrangement shown in the '259 patent will not work for current and future process technologies. This is particularly true at higher temperatures where the leakage current is very significant.
Another problem with current and future process technologies is gate leakage. NMOS transistor leakage is 5-10 time greater than PMOS gate leakage. If match transistor 25 shown in FIG. 3 of the '591 Patent is used in connection with a four transistor SRAM cell, such as cell 11, the gate leakage of transistors 16 and 17 will make the design more difficult.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.